TSMC State of the Art CMOS Technology
The technology industry has continued to witness new technological advancements. The innovations are intended to reduce costs and ensure efficiency. This research paper examines the processes that Taiwan Semiconductor Manufacturing Company Limited uses to develop products or services that make it noticeable in the technology industry in terms of process developments. Specifically, the study focuses on CMOS technology nodes targeting products, considering speed, power dissipation, area and types of interconnection.
Frequency of Operation (Speed)
The need to integrate more functions within a particular silicon area continues to enhance the trend of CMOS technology improvements. The steady down-scaling of feature sizes of CMOS technology has been the force behind continual improvement witnessed in circuit speed as well as cost per functionality for many years. Bamji and colleagues (2015) presented a detailed sign of the 512 x 424 time-of-flight system-on-chip (SoC) to be used in TSMC for 0.13 µm CMOS process. The process was designed to meet the demands of XBOX Microsoft Kinect that is appropriate when it relates to indoor requirements. The principle of an operation of a time-of-flight depth sensor is one of the strategies that have been used in explaining frequency of operation. This principle considers aspects such as signal amplitude that is transmitted by optical source and modulation frequency (Bamji et al., 2015). The time-of-flight sensor is critical for a signal to traverse the distance to the object. The amplitude of the received signal depends on factors such as power of the input light and reflectivity of the object. There is an on-chip mixing that is achieved through differential modulation of the quantum efficiency of the detectors in the pixel array. Notably, the quantum-efficiency-modulation detection can be performed at different input signal phases (Bamji et al., 2015). Such multiphase measurements yield various output values that enable calculation of phase angles for distances independent of the received signal amplitude. At low frequency, there is a less frequent wraparound that allows an extended range of operations without ambiguity in the measured distance (Bamji et al., 2015).
The time-of-flight SoC architecture has a sensor array that is comprised of 512 x 424 pixels. There are both top and bottom halves, each driven by separate clock drivers as well as pixel outputs for reading each separate half (Bamji et al., 2015). A high-speed internal oscillator is used to drive a clock generator to generate pixel clocks and modulation signal for the pixel clocks and light source modulation signals that are programmable.
High modulation contrast is achieved at high frequencies if a fabricated chip that uses a 0.13 µm mixed-signal low-power CMOS process with minor modifications supporting efficient time-of-flight operation is applicable (Bamji et al., 2015). The starting epi material is optimized in thickness as well as in dopant concentration to perform maximally. Special attention has to be paid to the avoidance of unforeseen effects and production of the required doping gradient. Dedicated implants steps are adopted in pixels to ensure that required work functions are set, and to provide suitable isolation alongside well profiles. Layers of aluminium metal are used to support front-side illumination as well as to facilitate pixel design, SoC integration, and power distribution. The addition of Microlenses has been done after processing CMOS and their design done with pixels in order to improve the effectiveness of the fill factor (Bamji et al., 2015). However, there has to be proper management of all optical interfaces to minimize reflection.
Client says about us
The service was excellent. I like 123helpme more and more each day because it makes my life a lot easier.
Hello. Thank you for the good work that you did with my writing assignment. I hope I won't need to use any kind of writing service in the future, but if I do, rest assured that it is your fine service that I will use. Please know that I am a satisfied customer, all the way, and that I will tell as many students as I can about the work that you do.
You did everything exactly as I asked. It was very important because now I know that you really listen. Thanks!
Thanks for helping me with the last 2 papers. The writer you've assigned to me complete my paper on time and with all requirements.
I was running out of time when I had to finish my coursework. This service made a great job with my coursework chapter so I managed to pass my paper in time. Totaly appreciate your service.
The time-of-flight pixels are designed to operate with a modulation contrast of 67.5 percent at 50 MHz, and there is also a responsitivity of 0.14 A/W at 860 nm (Bamji et al., 2015). This type of modulation contrast does not derive its power from active light neither it obtains it from ambient room lighting. The pixels, having been fully differential, create resistance to designing of issues that are familiar in non-multi-ended designs. Time-of-flight causes constraints on readout circuit similar to higher frame rate cameras. Importantly, multi-frequency and multi-phase operations will restrict the time available for light exposure for each image capture. A readout combines a 10 µm pitch column amplifier with a 40 µm pitch (Bamji et al., 2015). Readout speed doubles when independent readout circuits are dedicated to the top and bottom halves of the sensor array. Sensor designs with more than 200 mega pixel (s) readout capacity have been recorded as using column level ADC. The conclusion has been that a high-performance and high-resolution time-of-flight depth image sensor, which meets the needs of gaming applications or natural user interface, requires a sensor whose design is in a TSMC 0.13 µm CMOS process, consuming 2.1 W in a long-range large-FOV living room (Bamji et al., 2015). A high modulation contrast of 67 percent at 50 MHz of up to 130 MHz that uses a fully differential quantum efficiency modulation is necessary. Such a sensor allows high-dynamic-range operation through multigrain and multishutter (Bamji et al., 2015).
The Taiwan Semiconductor Manufacturing Company (TSMC) Limited had, in 2012, shipped 28 nm chip and expected to ship the 20 nm silicon chip by the end of 2014 or early 2015. The 20 nm chip was expected to be better than the existing 28 nm. The 28 nm chip generation has been highlighted as TSMC’s most energy-efficient as well as high-performance method of manufacturing to date. It was the first silicon chip that uses high-k metal (HKMG) process. The 28 nm technology can deliver twice the gate density of the previous 40 nm. The low power process was first available through the 28 nm technology (Taiwan Semiconductor Manufacturing Company Limited, n.d.). Consequently, it is considered ideal for low power standby applications, for instance, in cellular baseband. The technology has its speed improved by 20 percent over the previous (40 nm) process at the same gate.
The 28 nm technology features superior speed and performance, targeting GPU, CPU, PC, FPGA, networking, as well as consumer electronic applications. The 28 nm low power with high-k metal gates (HPL) technology uses the same gate stack of the HP technology, but it meets more strict low leakage requirements while maintaining the same speed (Taiwan Semiconductor Manufacturing Company Limited, n.d.). For instance, leakage and performance spectrum, N28HPL, is applicable for cellular baseband, such as wireless connectivity or programmable logics. Therefore, the 28 nm High Performance Mobile Computing (HPM) has been cited as appropriate for providing high performance for mobile applications in instances where there is a need for high speed. Through higher performance ability, the 28nm node is ideal for numerous applications, ranging from networking to high-end smartphones or mobile consumer products (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
TSMC also offers high performance compact mobile computing (HPC) for its customers. This is important, particularly at a time when the company intends to tap chip area as well as power-saving benefits of the mid-to-low end SoC designs. The 28HPC provides a 10 percent smaller die size as well as 30 percent more power reduction at all levels, this makes it better than the 28 LP (Taiwan Semiconductor Manufacturing Company Limited, n.d.). Moreover, the 28HPC IP ecosystem is comprehensive and compatible with 28HPM. This accelerates the time that the product needs to reach the market for customer’s use. Apart from smartphones, the 28HPC is also applicable in tablets and mobile consumer products (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
The TSMC’s 20nm process technology has been reported to provide 30 percent higher speed and 25 percent less power compared with the 28nm technology (Taiwan Semiconductor Manufacturing Company Limited, n.d.). The 20 nm is the main process that is used to drive various applications that run gamut in smartphones, tablets, desktops as well as servers. The 20 nm shows double digit 112Mb SRAM yields. This device is equipped with second-generation gate-last HKMG as well as third-generation silicon Germanium strain technology (Taiwan Semiconductor Manufacturing Company Limited, n.d.). By controlling the experience of the 28nm technology, the 20nm process optimizes the Back-end-of-line (BEOL) technology option. Through this technology, there has been deep collaboration with customers to ensure that the Moore’s Law continues a shrinking path (Taiwan Semiconductor Manufacturing Company Limited, n.d.). Production costs have been minimized and multiple customers’ IPs have also been verified on 20nm test chips. TSMC’s Open Innovation Platform design ecosystem empowers designers to optimize their projects, tools, as well as methodologies. At the 20 nm node, lithography techniques have had to change to overcome inbuilt resolution challenges. The design ecosystem consists of a robust design that enables IP suppliers to create enablement kits. Such kits are important because they support continuous improvements as well as interaction between designers for the sake of production success (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
TSMC’s 16FF+ (FinFET Plus) technology currently has the best technology features. Its FinFET transistors are supplemented with a third generation High-k/Metal Gate process. The transistor belongs to the fifth generation of transistor strain process. It also has an advanced 193-nm lithography area (Taiwan Semiconductor Manufacturing Company Limited, n.d.). Consequently, the 16nm technology has been able to offer significant power reduction using the same chip performance. This is critical for complex mobile applications as opposed to the traditional technologies that were built based on the planar structure.
Importantly, the TSMC’s 16FF+ technology is able to facilitate the provision of 65% higher speed compared to the 28HPM technology. The 16FF+ has been found to provide additional 40 percent higher speed as well as 60 percent power saving compared with the 20 SoC technology. Improving the 20SoC technology, the TSMC 16FF+ technology has the ability to share the same metal backend process with an aim to rapidly improve yields as well as display process maturity necessary for the value created from the start to the time when the product is delivered to the market (Taiwan Semiconductor Manufacturing Company Limited, n.d.). Considering the outstanding performance that FinFET has had, TSMC has been able to continue working with customers to reduce it or ensure creation of low power products. Through technological design innovation, costs had to be reduced or controlled. For instance, TSMC can now provide 9T as well as 7.5T cells that are applicable in mobile product chip area as well as power optimization. The 16FF+ test chips support multiple customers’ IP verification (Taiwan Semiconductor Manufacturing Company Limited, n.d.). The 16nm 3D-FinFET structure has been found to be different from the previous planar devices. Open innovation platform empowers designers to optimize their designs due to the presence of qualified IPs, design tools, and methodologies in TSMC’S 16nm technology (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
MOSFETs and Interconnect
The innovations observed in computing and mobile markets have continued remarkably to deliver more performance in smaller forms and factors, but with higher power efficiencies. Notably, the semiconductor technology has been one of the technologies enabling innovation because of its ability to provide a platform for building a System on a chip. The MOSFET transistor technology underlies the transistor technology today. However, a major challenge in using the MOSFET has been the short channel effects that have been affecting power in the planar form or leakage that unnecessarily increases idle power. This shortcoming hassled to power sensitive products in mobile and computing industries spending much of their lifespan in the off state (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
The challenges associated with MOSFET-based designs have led to the emergence of the FinFET. Indeed, this advancement of the MOSFET has been regarded as the best choice for next generation processes. TSMC has partnered with EDA leaders, such as Synopsis, to resolve design complexities of FinFET. It is also important to note that FinFET is a three-dimensional device. A FinFet consists of fins, which form its source as well as drain portion of the capacitor and provide the channel for a current to flow any time the switch is on. It has a gate that controls the switching operation by wrapping around the three-dimensional structure (Taiwan Semiconductor Manufacturing Company Limited, n.d.).
You can ask us “write my descriptive essay” on this or any other topic at 123HelpMe.org. Don’t waste your time, order now!
FinFET are often called multi-gate transistors because a thin vertical fin is controlled by the gate that originates from three sides. In the FinFET devices, interconnection is possible across the 16nm process, including front-end-of-line (FEOL), back-end-of-line (BEOL), and middle-end-of-line (MEOL). FEOL focuses on device transistor formation, and the features of the technology have invariant design or layout. MEOL entails intermediate steps that complete the formation of transistors before contacts. BEOL refers to the processing steps that lead to the formation of contact and interconnect. In this process, modeling becomes independent of the FinFET device process effects. However, it incorporates interconnect parasitic effects only of Taiwan Semiconductor Manufacturing Company Limited, n.d.).
This research paper has examined the state of the CMOS technology of Taiwan Semiconductor Manufacturing Company Limited. Throughout the years, the company has continued to improve its existing technologies to ensure that customers or product developers obtain value for their purchases. TSMC has collaborated with other technology companies to innovate processes that reduce costs and consume less power. Therefore, it is not surprising to see the company’s processes being applied in smartphone, tablet and desktop technologies.